Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level
暂无分享,去创建一个
Yoshiyuki Yashima | Ken Nakamura | Mitsuo Ikeda | Jiro Naganuma | Makoto Endo | Hiroe Iwasaki | Takeshi Yoshitome | Yasuyuki Nakajima | Koyo Nitta | Takayuki Onishi | Toshihiro Minami | Mitsuo Ogura | Yutaka Tashiro | Y. Yashima | Takayuki Onishi | Hiroe Iwasaki | M. Ikeda | T. Yoshitome | Y. Nakajima | J. Naganuma | M. Endo | Y. Tashiro | K. Nitta | K. Nakamura | T. Minami | Mitsuo Ogura
[1] Yoshiyuki Yashima,et al. New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI , 2005, IEEE Transactions on Consumer Electronics.
[2] Kazuhiro Maeda,et al. An advanced multimedia processing LSI suitable for HDTV applications , 2001, IEEE Trans. Consumer Electron..
[3] Yoshiyuki Yashima,et al. Super high resolution video codec system with multiple MPEG-s HDTV codec LSI's , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[4] T. Minami. A single-chip MPEG2 MP@ML video encoder with multi-chip configuration for a single-board MP@HL encoder , 1998 .
[5] Y. Nakajima,et al. An MPEG-2 encoding PC card system for real-time mobile applications , 2000, 2000 Digest of Technical Papers. International Conference on Consumer Electronics. Nineteenth in the Series (Cat. No.00CH37102).
[6] Yoshiyuki Yashima,et al. MPEG2 video and audio codec board set for a personal computer , 1995, Proceedings of GLOBECOM '95.
[7] T. Yoshizawa,et al. A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).
[8] I. Tamitani,et al. A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking , 1997, IEEE J. Solid State Circuits.
[9] Toshio Kondo,et al. An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[10] Yoshiyuki Yashima,et al. A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[11] Tughrul Arslan,et al. Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[12] Yasuyuki Okumura,et al. An MPEG2-based digital CATV and VOD system using ATM-PON architecture , 1996, Proceedings of the Third IEEE International Conference on Multimedia Computing and Systems.
[13] KondoToshio,et al. Two-Chip MPEG-2 Video Encoder , 1996 .
[14] Ken Nakamura,et al. A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[15] H. Kodama,et al. A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[16] Ken Nakamura,et al. Development of an HDTV MPEG-2 encoder based on multiple enhanced SDTV encoding LSIs , 2001, ICCE. International Conference on Consumer Electronics (IEEE Cat. No.01CH37182).
[17] 児玉 知也,et al. A Single-Chip MPEG-2 Codec Based on Customizable Media Microprocessor , 2002 .