On-chip 20Gbps high-speed I/O IC test system for signal integrity characterization in flip-chip package

This paper focuses on signal integrity characterization using On-chip 20Gbps high-speed I/O embedded test structures in a flip-chip package. The authors designed On-chip 20Gbps High-Speed I/O Test IC that consists of 20GHz PLL (Phase Locked Loop), 20Gbps PRBS (Pseudo Random Bit Sequence) Generator and 4-port 20Gbps differential CML (Current Mode Logic) I/O. The test IC is designed and simulated in UMC 90nm technology. In addition, the author modeled a test vehicle on to Android Rogers 4350B PCB which is 50Ω matched in HFSS. The vehicle has two patterns; one is a differential microstrip lines pattern which has two different lengths of differential pair traces, the other is differential microstrip lines with multiple vias. Using the test IC and the vehicle, the paper is presented both transient and electromagnetic simulation results for characterizing the signal integrity in flip-chip package.

[1]  Deog-Kyoon Jeong,et al.  Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  A. Tuszynski,et al.  CMOS tapered buffer , 1990 .

[3]  W. R. Eisenstadt,et al.  S-parameter-based IC interconnect transmission line characterization , 1992 .

[4]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[5]  W. R. Eisenstadt,et al.  GTL high speed I/O in 3D ICs for TSV and interconnect signal integrity characterization , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[6]  Yanping Ding,et al.  A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS , 2007, IEEE Journal of Solid-State Circuits.

[7]  M. Bayer,et al.  Cell based fully integrated CMOS frequency synthesizers , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[8]  V. Zlatkovic,et al.  Clocking Challenges in High Speed Source Synchronous Interfaces , 2006, 2006 25th International Conference on Microelectronics.