论文信息 - A non-feedback multiphase clock generator

A non-feedback multiphase clock generator

This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 /spl mu/m, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz.

Yijun Zhou | Lixin Yang | Jiren Yuan

[1] Yiu-Fai Chan,et al. A portable digital DLL for high-speed CMOS interface circuits , 1999, IEEE J. Solid State Circuits.

[2] M. Mitsuishi,et al. A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand" , 2000, IEEE Journal of Solid-State Circuits.