Asynchronous logics and application to information processing

The limiting numbe! of switching elements to which any given switching element may �upply �Ign�S has been tenned the "fan-out" of the element. Whenever logical .design IS undertaken, such fan-out restrictions must be ob­ served by th . e desIgne�, and the conditions imposed by these restrictions are usually consIdered qUIte separately from the logical conditions of the design. However, the spe�ds of 10gIC� ele�ents in .a switching system have long been known to bear an Inverse reiattonship to theIr fan-out. This inverse relationship results from the fact that both speed and fan-out place conflicting requirements upon the power amplification of the element. In parallel computers, for ex­ ample, one of the gr�atest limitations in speed occurs when signals from the control must be amplified and sent to all the gates in a register. This amplifica­ tion is perfonned whenever a word is transferred from one register to another, and, in particular, it limits the speed of such operations as shifting and multi­ plication, which involve a large number of such transfers. Circuit designers have recognized the fact that computation speed is often limited by the time required to amplify control signals and transmit them to the registers, and so have tended to concentrate upon the design of fast cable drivers and gate drivers rather than upon the design of flip-flops and other logical elements whose individual speeds have relatively little influence upon the speed of computation. On the other hand, logical designers and system designers have not usually been influenced by such considerations of the effect of fan-out upon speed, or at least not to the same extent, and the methods used for carrying out calculations and for performing arithmetic have remained unaffected. In the present discussion a method of logical design will be proposed that is based upon the notion that fan-out is always limited and that calculation time depends upon the amount of amplification that .must be performed. AI!hough the method will be described from the standpomt of asynchronous lOgICS, the basic problem is common to both asynchronous and synchronous systems, and a variation of the method may be derived that applies to synchronous systems. However, when the procedure is used for the design of an a�ynchronous system the methods used automatically ensure that the result WIll be speed­ independent. Hence no special precautions need b� taken during design to make certain that the course followed by the calculatIOn does not depend upon the speeds of the logical switching elements.