Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs
暂无分享,去创建一个
[1] Luca Benini,et al. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.
[2] Soha Hassoun,et al. Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs , 2009, 2009 IEEE International Conference on 3D System Integration.
[3] S. Yoon,et al. High RF performance TSV silicon carrier for high frequency application , 2008, 2008 58th Electronic Components and Technology Conference.
[4] J. Yuan,et al. Substrate noise coupling in mixed-signal ICs , 1998, Proceedings IEEE Southeastcon '98 'Engineering for a New Era'.
[5] Makoto Motoyoshi,et al. Through-Silicon Via (TSV) , 2009, Proceedings of the IEEE.
[6] Shijian Luo,et al. 3D Integration-Present and Future , 2008, 2008 10th Electronics Packaging Technology Conference.
[7] Katsuyuki Sakuma,et al. Three-dimensional silicon integration , 2008, IBM J. Res. Dev..
[8] Ali Afzali-Kusha,et al. Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation , 2006, Proceedings of the IEEE.
[9] Lei Jiang,et al. Die Stacking (3D) Microarchitecture , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[10] Patrick Leduc,et al. Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology , 2009, 2009 European Microelectronics and Packaging Conference.
[11] Joungho Kim,et al. Active circuit to through silicon via (TSV) noise coupling , 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.
[12] Mitsumasa Koyanagi,et al. Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs , 2008 .
[13] Paresh Limaye,et al. Design issues and considerations for low-cost 3D TSV IC technology , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[14] Alan F. Murray,et al. IEEE International Solid-State Circuits Conference , 2001 .
[15] Jian Xu,et al. Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.