A 58-dBm $S$ -Band Limiter in Standard 0.25- $\mu\hbox{m}$ BiCMOS Technology

A series of limiters have been developed for power levels up to 58 dBm in a standard 0.25- μm BiCMOS process. After a thorough analysis of general design tradeoffs, a figure-of-merit (FOM) for limiter technologies is introduced. This FOM indicates the necessity of a high current-to-capacitance ratio, which is obtained by exploiting the base-collector junction. Two designs were implemented for operation up to S- and X-band with optimized power capability for the respective frequency bands. The proposed designs avoid dedicated technologies like PIN-diodes or gas discharge tubes and thus enable integration of the limiter in a receiver front-end chip. The limiters have been designed based on a diode model, which was carefully extracted from measurements on a single diode cell. Reliability aspects, specific to limiters, are discussed. The measurements on the S-band limiter showed that 58 dBm pulses with 10-μs length can be handled, which is similar to power levels obtained by commercial PIN diode limiters.

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