Performance of the VAX-11/780 translation buffer: simulation and measurement

A virtual-address translation buffer (TB) is a hardware cache of recently used virtual-to-physical address mappings. The authors present the results of a set of measurements and simulations of translation buffer performance in the VAX-11/780. Two different hardware monitors were attached to VAX-11/780 computers, and translation buffer behavior was measured. Measurements were made under normal time-sharing use and while running reproducible synthetic time-sharing work loads. Reported measurements include the miss ratios of data and instruction references, the rate of TB invalidations due to context switches, and the amount of time taken to service TB misses. Additional hardware measurements were made with half the TB disabled. Trace-driven simulations of several programs were also run; the traces captured system activity as well as user-mode execution. Several variants of the 11/780 TB structure were simulated.

[1]  Margaret J. Giannini.  Computing and the Handicapped: A Promising Alliance , 1981, Computer.

[2]  William D. Strecker,et al.  VAX-11/780 - A virtual address extension to the DEC PDP-11 family , 1899, AFIPS National Computer Conference.

[3]  Leonard J. Shustek,et al.  An instruction timing model of CPU performance , 1977, ISCA '77.

[4]  Michael C. L. Chow,et al.  P32-bit processor chip integrates major system functions , 1983 .

[5]  Gene McDaniel.  An analysis of a mesa instruction set using dynamic instruction frequencies , 1982, ASPLOS I.

[6]  Michael D. Schroeder,et al.  Performance of the GE-645 associative memory while Multics is in operation , 1971, SIGOPS Workshop on System Performance Evaluation.

[7]  Henry M. Levy,et al.  Computer Programming and Architecture: The VAX-11 , 1980 .

[8]  Marshall D. Abrams,et al.  Survey of remote terminal emulators , 1977 .

[9]  Henry M. Levy,et al.  Virtual Memory Management in the VAX/VMS Operating System , 1982, Computer.

[10]  Douglas W. Clark,et al.  Cache Performance in the VAX-11/780 , 1983, TOCS.

[11]  H. J. Greenbaum,et al.  A SIMULATOR OF MULTIPLE INTERACTIVE USERS TO DRIVE A TIME-SHARED COMPUTER SYSTEM , 1969 .

[12]  W ClarkDouglas,et al.  Performance of the VAX-11/780 translation buffer , 1985 .

[13]  Cheryl A. Wiecek,et al.  A case study of VAX-11 instruction set usage for compiler execution , 1982, ASPLOS I.

[14]  Peter J. Denning,et al.  On modeling program behavior , 1972, AFIPS '72 (Spring).

[15]  Alan Jay Smith,et al.  Cache Memories , 1982, CSUR.

[16]  Robert O. Winder,et al.  Cache-based Computer Systems , 1973, Computer.

[17]  Lawrence J. Kenah,et al.  VAX/VMS internals and data structures , 1984 .

[18]  Andris Padegs,et al.  Architecture of the IBM system/370 , 1978, CACM.

[19]  Mahadev Satyanarayanan,et al.  Design Trade-Offs in VAX-11 Translation Buffer Organization , 1981, Computer.