Chaotic behavior and synchronization phenomena in a novel chaotic transistors circuit

The chaotic behavior and synchronization phenomena which occur in a novel chaotic transistors circuit with high speed operation are described. The most important point is to change a nonlinear transfer characteristic of a MOS inverter to a nonlinearity generating chaos. The proposed circuit includes a looped MOS inverter having a pull-up resistor serially connected to a pull-down NMOS transistor. A switched-capacitor (SC) circuit having a hold capacitor and two CMOS switches is added in the loop of the circuit to operate sampling holding. The chaotic behavior has been found along with a variation of a sampling clock frequency. The synchronization phenomena is also found between two coupled chaotic transistors circuits. The test chip is implemented employing 2 /spl mu/m CMOS technology of the MOSIS service.

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