A Novel System-Level Power Integrity Transient Analysis Methodology using Simplified CPM Model, Physics-based Equivalent Circuit PDN Model and Small Signal VRM Model

The goal of a well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise and errors delivered to chip. This paper provides power integrity engineers a guideline to model PDN agilely in a simplified method and choose specific voltage regulator module model under specific circumstances. These comparisons and studies present the advantage of this novel methodology using equivalent circuit model for system level power integrity transient analysis.

[1]  A. Waizman,et al.  Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology , 2001 .

[2]  Zhiping Yang.  Fundamentals of power integrity , 2017, 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI).

[3]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[4]  W. Marsden.  I and J , 2012 .

[5]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[6]  Peter Boyle,et al.  System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[7]  Larry D. Smith,et al.  Power distribution system design methodology and capacitor selection for modern CMOS technology , 1999 .

[8]  Kenji Araki,et al.  Improved Target Impedance for Power Distribution Network Design With Power Traces Based on Rigorous Transient Analysis in a Handheld Device , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[9]  Soo-Won Kim,et al.  Simplified Chip Power Modeling Methodology Without Netlist Information in Early Stage of SoC Design Process , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[10]  Shuo Wang,et al.  Investigating a Guard Trace Ring to Suppress the Crosstalk due to a Clock Trace on a Power Electronics DSP Control Board , 2014, IEEE Transactions on Electromagnetic Compatibility.

[11]  Celina Gazda.  Electromagnetic Compatibility and Signal Integrity Aware Modeling and Design of Electronic Circuits ('Elektromagnetische compatibiliteits- en signaalintegriteitsbewust modelleren en ontwerpen van elektronische schakelingen'). , 2012 .

[12]  Dan Oh,et al.  Improving the target impedance method for PCB decoupling of core power , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).