A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology

ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have been used for several megabit test-chips and memory macros [1-3]. This paper presents a MeOx-based 32Gb ReRAM test chip developed in 24nm technology.

[1]  Chang Hua Siau,et al.  A 0.13µm 64Mb multi-layered conductive metal-oxide memory , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  B. Kleveland,et al.  512 Mb PROM with 8 layers of antifuse/diode cells , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  Yukio Hayakawa,et al.  An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput , 2012, IEEE Journal of Solid-State Circuits.

[4]  G. Palumbo,et al.  Charge-pump circuits: power-consumption optimization , 2002 .

[5]  Shoji Sakamoto,et al.  An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput , 2012, 2012 IEEE International Solid-State Circuits Conference.