FPGA implementation of unsigned multiplier circuit based on quaternary signed digit number system

Digital systems are mainly used in data processing, control systems and computation. They are having numberof advantages over analog system: one of advantage is fast arithmetic operation. There are different techniques for performing arithmetic operations such as Binary Signed Digit(BSD), Wallace, Booth multiplication etc. Using binary number system for arithmetic operation generates carry which creates delay and reduce the speed of operation. To overcome this problem we are using higher radix number system such as Quaternary Signed Digit (QSD). QSD number system is base 4 number system. QSD is represented by decimal numbers as : 0, 1, 2 and 3. It is responsible for carry free arithmetic operations. In this paper we proposed a high speed, low power QSD multiplier which is capable of doing carry free operation. This circuit can multiply both signed and unsigned numbers without any extra delay. This circuit also increases the speed of operation and is less complex. The circuit is simulated on XilinxSPARTAN 3E-100or250 field programmable gate array (FPGA) board using Verilog HDL.