A 10-bit 5MS/s successive approximation ADC cell in 1.2μm CMOS

A 10-bit 5MS/s successive approximation ADC cell is presented. With a clock frequency of 70MHz, the sampling time is limited to 14nS, which is aimed for a parallel ADC array. A two-step principle based on unsymmetrical dualcapacitor charge-redistribution-coupling has been used. The comparator with the help of reset function presents a fast response to the successive comparison. The core of the ADC cell occupies an area of 0.6mm2 and consumes a power of 18mW while the chip consumes a total power of 32 mW.