FPGA implementation of AES algorithm for high throughput using folded parallel architecture

This paper presents high throughput architecture for the hardware implementation of Advanced Encryption Standard algorithm. Advanced Encryption Standard is the industry standard crypto algorithm for encryption and is used for protecting secret information. This work is mainly targeted for low-cost embedded applications. This paper introduces parallel operation in the folded architecture to obtain better throughput. The design is coded in Very High-speed Integrated Circuit Hardware Description Language. Timing simulation is performed to verify the functionality of the designed circuit. The proposed structure is implemented in Virtex-6 XC6VLX75T FPGA device. This work gives a high throughput of 37.1Gb/s with a maximum frequency of 505.5MHz, which is 20% higher than the maximum throughput reported in the literature. Copyright © 2012 John Wiley & Sons, Ltd.

[1]  M. C. Liberatori,et al.  AES-128 cipher: Minimum area, low cost FPGA implementation , 2007 .

[2]  Miguel A. Vega-Rodríguez,et al.  A new methodology to implement the AES algorithm using partial and dynamic reconfiguration , 2010, Integr..

[3]  Jean-Jacques Quisquater,et al.  Implementation of the AES-128 on Virtex-5 FPGAs , 2008, AFRICACRYPT.

[4]  John V. McCanny,et al.  Rijndael FPGA implementation utilizing look-up tables , 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

[5]  Seong-Moo Yoo,et al.  AES crypto chip utilizing high-speed parallel pipelined architecture , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[6]  Jean-Didier Legat,et al.  Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs , 2003, CHES.

[7]  Odysseas G. Koufopavlou,et al.  Architectures and VLSI Implementations of the AES-Proposal Rijndael , 2002, IEEE Trans. Computers.

[8]  Milos Drutarovský,et al.  Two Methods of Rijndael Implementation in Reconfigurable Hardware , 2001, CHES.

[9]  Seong-Moo Yoo,et al.  An AES crypto chip using a high-speed parallel pipelined architecture , 2005, Microprocess. Microsystems.

[10]  K. Vu.  FPGA Implementation, AES for CCM Mode Encryption Using Xilinx Spartan-II , 2003 .

[11]  Alok N. Choudhary,et al.  Exploring Area/Delay Tradeoffs in an AES FPGA Implementation , 2004, FPL.

[12]  Antonino Mazzeo,et al.  An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm , 2003, FPL.

[13]  Chih-Peng Fan,et al.  FPGA IMPLEMENTATIONS OF HIGH THROUGHPUT SEQUENTIAL AND FULLY PIPELINED AES ALGORITHM , 2008 .

[14]  Ingrid Verbauwhede,et al.  A hardware implementation in FPGA of the Rijndael algorithm , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[15]  Sheikh Muhammad Farhan.  High Data Rate 8-Bit Crypto Processor , 2004, ISSA.

[16]  Keshab K. Parhi,et al.  High-speed VLSI architectures for the AES algorithm , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  John Waldron,et al.  AES Encryption Implementation and Analysis on Commodity Graphics Processing Units , 2007, CHES.

[18]  Kris Gaj,et al.  Very Compact FPGA Implementation of the AES Algorithm , 2003, CHES.

[19]  Tim Good,et al.  AES on FPGA from the Fastest to the Smallest , 2005, CHES.

[20]  Shuenn-Shyang Wang,et al.  An efficient FPGA implementation of advanced encryption standard algorithm , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[21]  Franc Novak,et al.  HARDWARE IMPLEMENTATION OF AES ALGORITHM , 2005 .

[22]  M. SIRIN KUMARI,et al.  HIGH THROUGHPUT-LESS AREA EFFICIENT FPGA IMPLEMENTATION OF BLOCK CIPHER AES ALGORITHM , 2011 .

[23]  Francisco Rodríguez-Henríquez,et al.  4.2 Gbit/s single-chip FPGA implementation of AES algorithm , 2003 .

[24]  Jean-Didier Legat,et al.  Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[25]  Arshad Aziz,et al.  HARDWARE IMPLEMENTATION OF AES-CCM FOR ROBUST SECURE WIRELESS NETWORK , 2005 .

[26]  Francisco Rodríguez-Henríquez,et al.  AES algorithm implementation - an efficient approach for sequential and pipeline architectures , 2003, Proceedings of the Fourth Mexican International Conference on Computer Science, 2003. ENC 2003..

[27]  Jean-Didier Legat,et al.  A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL , 2003, FPGA '03.

[28]  Ahmed Moussa,et al.  Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA , 2009, ArXiv.

[29]  Matti Tommiska,et al.  A fully pipelined memoryless 17.8 Gbps AES-128 encryptor , 2003, FPGA '03.

[30]  Ingrid Verbauwhede,et al.  Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors , 2006, IEEE Transactions on Computers.

[31]  F. Rodríguez-Henríquez,et al.  4.2 Gbits/sec Single-chip Fpga Implementation of the Aes Algorithm , 2004 .

[32]  Ingrid Verbauwhede,et al.  A 21.54 Gbits/s fully pipelined AES processor on FPGA , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[33]  Min Wang,et al.  How Well Are High-End DSPs Suited for the AES Algorithms? AES Algorithms on the TMS320C6x DSP , 2000, AES Candidate Conference.

[34]  Saudi Arabia,et al.  Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA , 2009 .

[35]  Arshad Aziz,et al.  An Efficient Software Implementation of AES-CCM for IEEE 802.11i Wireless St , 2007, 31st Annual International Computer Software and Applications Conference (COMPSAC 2007).

[36]  Panu Hämäläinen,et al.  Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[37]  S.A. Manavski,et al.  CUDA Compatible GPU as an Efficient Hardware Accelerator for AES Cryptography , 2007, 2007 IEEE International Conference on Signal Processing and Communications.

[38]  Murat Askar,et al.  A high speed FPGA implementation of the Rijndael algorithm , 2004 .

[39]  Ingrid Verbauwhede,et al.  Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm , 2001, CHES.

[40]  Norbert Felber,et al.  Multi-gigabit GCM-AES Architecture Optimized for FPGAs , 2007, CHES.