Impact of I/O buffer configuration on the ESD performance of a 0.5 /spl mu/m CMOS process

The authors consider the ESD performance of various I/O buffer configurations implemented with a general purpose, triple-metal, silicided diffusion, 0.5 /spl mu/m LDD CMOS process. More specifically, several I/O configurations are studied and, in addition to that, the influence of specific process steps (i.e. over-doped p-well) to the ESD performance are also addressed. Finally, it is demonstrated that the configuration which guarantees an ESD performance over 8 kV consists of a clamp formed on an over-doped p-well between pad and Vss, a diode in-between pad and Vdd and a similar clamp between the power and ground supplies.