A real-time feedback double-sector controller (RTFB DSC) for the APS Upgrade has been under design for the past year. Using the Xilinx Zynq-7000 All Programmable System on a Chip FPGA residing on the ZC706 board as the base platform, the upgrade path interfaces to the existing accelerator system and modernizes the beam position monitoring and feedback systems. The modernized system increases the RTFB system sample rate from 1.5 kHz to 22.6 kHz. We report the plan for sector-by-sector upgrades that will occur during system shutdowns and allow the upgraded sectors to operate with the existing sectors. The mapping of the RTFB DSC architecture is shown utilizing the targeted FPGA features. These features include the dual ARM Cortex A9 processors, multi-port DDR3 memory controllers, gigabit transceivers, and the programming logic interconnect for implementing advanced orbit feedback controller algorithms using floating-point DSP operations. The RTFB DSC FPGA architecture is revealed as well as subsequent progress on the chassis implementation.