High efficiency, high gain power transistors are required to meet RF performance and output specifications as new generation portable communication products move towards lower voltage operations. A low cost, high efficiency silicon MOSFET using RFLDMOS (LV2) technology was developed in Motorola to operate at 3.4-12.5 V drain voltages. The LV2 device can deliver 70% power added efficiency with 12 dB gain, 31.5 dBm output power at 3.4 V and 850 MHz. This is the best known RF performance for silicon devices at 3.4 V. This paper focuses on 3.4 V LV2 device optimization and performance.