A V-Band MMIC Doubler Using a 4th Harmonic Mixing Technique

A V-band frequency doubler consisting of a harmonics generating stage and a mixing-amplifying stage is proposed. In the first stage, a common source-common gate (CS-CG) topology is deployed to attenuate the odd order harmonics. A common source transistor is implemented in the second stage to amplify the 2nd harmonic and down convert the fourth harmonic to the desired second harmonic frequency. This transistor is biased in the nonlinear regime. The in-phase addition of 2nd harmonics generated by amplifying and mixing mechanisms improves the overall conversion gain and power added efficiency (PAE) of the doubler. A proof-of-concept circuit is designed and manufactured in a 0.1-μm GaAs pHEMT technology. The proposed doubler demonstrates up to 35 dBc rejection ratio of undesired harmonics while it shows a conversion gain of 9.2 dB. The doubler consumes dc power of 146 mW and achieves a peak PAE of 20%.

[1]  Ming-Lin Chuang.  Dual-Band Impedance Transformer Using Two-Section Shunt Stubs , 2010, IEEE Transactions on Microwave Theory and Techniques.

[2]  Chih-Chun Shen,et al.  Design and Analysis of a $Ka$-Band Monolithic High-Efficiency Frequency Quadrupler Using GaAs HBT–HEMT Common-Base/Common-Source Balanced Topology , 2013, IEEE Transactions on Microwave Theory and Techniques.

[3]  Yong-Zhong Xiong,et al.  A 27–41 GHz Frequency Doubler With Conversion Gain of 12 dB and PAE of 16.9% , 2012, IEEE Microwave and Wireless Components Letters.

[4]  A. Leuther,et al.  A D-band frequency doubler MMIC based on a 100-nm metamorphic HEMT technology , 2005, IEEE Microwave and Wireless Components Letters.

[5]  Herbert Zirath,et al.  A High Power-Efficiency D-Band Frequency Tripler MMIC With Gain Up to 7 dB , 2014, IEEE Microwave and Wireless Components Letters.

[6]  Hong-Yeh Chang,et al.  A Broadband High Efficiency High Output Power Frequency Doubler , 2010, IEEE Microwave and Wireless Components Letters.

[7]  Huei Wang,et al.  A broadband PHEMT MMIC distributed doubler using high-pass drain line topology , 2004 .

[8]  Chul Soon Park,et al.  A Low-Power, High-Suppression V-band Frequency Doubler in 0.13 $\mu$ m CMOS , 2008, IEEE Microwave and Wireless Components Letters.

[9]  Ziqiang Yang,et al.  A 3–50 GHz Ultra-Wideband PHEMT MMIC Balanced Frequency Doubler , 2008, IEEE Microwave and Wireless Components Letters.