Degradation analysis of high performance 14nm FinFET SRAM

Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1% degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3% increase only; a relative difference of 25%, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58%.)

[1]  B. Parvais,et al.  Defect-based compact modeling for RTN and BTI variability , 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

[2]  G. Groeseneken,et al.  Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.

[3]  Michael Nicolaidis,et al.  Reliability challenges of real-time systems in forthcoming technology nodes , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Francky Catthoor,et al.  Bias Temperature Instability analysis of FinFET based SRAM cells , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  Hao-I Yang,et al.  Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Shekhar Y. Borkar.  Microarchitecture and Design Challenges for Gigascale Integration , 2004, MICRO.

[7]  S. P. Park,et al.  Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance , 2007, ICCAD 2007.

[8]  Andrew R. Brown,et al.  Impact of NBTI/PBTI on SRAM Stability Degradation , 2011, IEEE Electron Device Letters.

[9]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[10]  Ching-Te Chuang,et al.  Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability , 2009, Microelectron. Reliab..

[11]  Francky Catthoor,et al.  Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[12]  Francky Catthoor,et al.  Read path degradation analysis in SRAM , 2016, 2016 21th IEEE European Test Symposium (ETS).

[13]  Mehdi Baradaran Tahoori,et al.  Aging mitigation in memory arrays using self-controlled bit-flipping technique , 2015, The 20th Asia and South Pacific Design Automation Conference.

[14]  Hamid Mahmoodi,et al.  Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[15]  Ilia Polian,et al.  Analyzing the effects of peripheral circuit aging of embedded SRAM architectures , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[16]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).