Low complexity QR-decomposition architecture using the logarithmic number system

In this paper we propose a QR-decomposition hardware implementation that processes complex calculations in the logarithmic number system. Thus, low complexity numeric format converters are installed, using nonuniform piecewise and multiplier-less function approximation. The proposed algorithm is simulated with several different configurations in a downlink precoding environment for 4×4 and 8×8 multi-antenna wireless communication systems. In addition, the results are compared to default CORDIC-based architectures. In a second step, HDL implementation as well as logical and physical CMOS synthesis are performed. The comparison to actual references highlight our approach as highly efficient in terms of hardware complexity and accuracy.

[1]  Dirk Wübben,et al.  Low Complexity Successive Interference Cancellation for Per-Antenna-Coded MIMO-OFDM Schemes by Applying Parallel-SQRD , 2006, 2006 IEEE 63rd Vehicular Technology Conference.

[2]  E. V. Krishnamurthy,et al.  On Computer Multiplication and Division Using Binary Logarithms , 1963, IEEE Transactions on Electronic Computers.

[3]  Robert C. Aitken,et al.  Low Power Methodology Manual - for System-on-Chip Design , 2007 .

[4]  Robert H. Halstead,et al.  Matrix Computations , 2011, Encyclopedia of Parallel Computing.

[5]  Hubert Kaeslin,et al.  Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication , 2008 .

[6]  Robert F. H. Fischer,et al.  Precoding and Signal Shaping for Digital Transmission , 2002 .

[7]  Jack E. Volder,et al.  The CORDIC computing technique , 1899, IRE-AIEE-ACM '59 (Western).

[8]  P. Glenn Gulak,et al.  A low-complexity high-speed QR decomposition implementation for MIMO receivers , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[9]  Gene H. Golub,et al.  Matrix computations (3rd ed.) , 1996 .

[10]  Jean-Michel Muller,et al.  Elementary Functions: Algorithms and Implementation , 1997 .

[11]  Wolfgang Fichtner,et al.  Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[12]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[13]  J. Detrey,et al.  A VHDL library of LNS operators , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[14]  Jean-Michel Muller,et al.  Elementary functions - algorithms and implementation (2. ed.) , 2006 .

[15]  Pei-Yun Tsai,et al.  Efficient Implementation of QR Decomposition for Gigabit MIMO-OFDM Systems , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Davide De Caro,et al.  Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  A. Burg,et al.  Matrix Decomposition Architecture for MIMO Systems: Design and Implementation Trade-offs , 2007, 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers.

[18]  J. Muller.  Elementary Functions, Algorithms and Implementation, 2nd Edition , 2006 .

[19]  Gu-Yeon Wei,et al.  The Accelerator Store framework for high-performance, low-power accelerator-based systems , 2010, IEEE Computer Architecture Letters.