Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (Sol) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted Sol nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOL The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure. (C) 2005 Elsevier Ltd. All rights reserved.

[1]  Denis Flandre,et al.  Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits , 1996 .

[2]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[3]  Denis Flandre,et al.  Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects , 2000 .

[4]  Eddy Simoen,et al.  Simple method for the determination of the interface trap density at 77 K in fully depleted accumulation mode SOI MOSFETs , 1993 .

[5]  Denis Flandre,et al.  Analog performance and application of graded-channel fully depleted SOI MOSFETs , 2000 .

[6]  Denis Flandre,et al.  Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .

[7]  Mohamed A. Osman,et al.  Zero-temperature-coefficient biasing point of partially depleted SOI MOSFET's , 1995 .

[8]  R. E. Thomas,et al.  Carrier mobilities in silicon empirically related to doping and field , 1967 .

[9]  Ashok K. Goel,et al.  Zero-Temperature-Coefficient Biasing Point of a Fully-Depleted SOI MOSFET , 2002, Computers and Their Applications.

[10]  L. Rubin.  Low Temperature Electronics: Physics, Devices, Circuits, and Applications , 2002 .

[11]  Denis Flandre,et al.  An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics , 1999 .

[12]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[13]  Gerard Ghibaudo,et al.  Analysis and modeling of self-heating effects in thin-film SOI MOSFETs as a function of temperature , 1995 .

[14]  Denis Flandre,et al.  Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs , 1994 .

[15]  Denis Flandre,et al.  Subthreshold slope of long-channel accumulation-mode p-channel SOI MOSFETs , 1994 .

[16]  M. J. Deen,et al.  Operational characteristics of CMOS op-amps at cryogenic temperatures , 1988 .