A Novel Intra Prediction Architecture for the Hardware HEVC Encoder

This work presents a novel Intra prediction architecture for the hardware High Efficiency Video Coding (HEVC) encoder. The architecture supports full range of features included in the standard, in accordance with the Main and Main 10 profiles, i.e. all modes and all Prediction Unit (PU) sizes. The architecture embeds the internal RAM working at the doubled clock rate to provide quick access to reference samples. This also leads to a reduction of required number of registers, while maintaining a high throughput. All needed multiplications are carried out using multiplexers and adders. The module provides a few soft configuration options, allowing the encoder to skip some modes and PU sizes. This feature trades computation time for compression efficiency. The module can produce 8x8 prediction blocks almost in each clock cycle. The design can operate at 100 MHz and 200 MHz for FPGA Aria II devices and the TSMC 0.13μm technology, respectively. The implementations generating all allowable predictions are able to process almost 15 and 30 frames per second for 1080p sequences for FPGA and ASIC, respectively. When 4x4 predictions are off, the trough put is doubled.