Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks

The impact of MOSFET source/drain junction scaling on the ESD robustness of shallow trench isolation (STI)-defined diode structures is shown for the first time. ESD robustness improvements to STI-bound p/sup +/ diodes using germanium preamorphization and deep B11 implants, and polysilicon-bordered ESD networks are also discussed.

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