To enable cost-effective shrink of future devices, a new High-NA EUV platform is being developed. The High-NA EUV scanner employs a novel POB design concept with 0.55NA that enables 8nm HP resolution and a high throughput.
In this paper we will discuss the imaging performance and technology solutions to support our customers device roadmap from High-NA insertion towards low-k1 extension for critical Logic/MPU and DRAM layers. We will address various technology solutions that enable a high contrast through focus for decreasing feature size, such as mask stack optimization, computational litho solutions and advanced illumination shapes.