Network-on-Chip: A State-of-the-art Review

Large scale System-on-Chip (SoC) has been enabled by the scaling of microchip technologies. As data intensive applications have emerged and processing power has increased, the threat of the communication components on single-chip systems introduced network on chip (NoC). NoC provides the concept of interachip communication. In this paper a study treats an outstanding concept for system-on-chip communication introduced as communication network on-chip (NoC). This paper includes the NoC basics, network topology, relevant research issues and different abstraction levels.

[1]  Kees G. W. Goossens,et al.  An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[2]  William J. Dally,et al.  Smart Memories: a modular reconfigurable architecture , 2000, ISCA '00.

[3]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[4]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[5]  Steven M. Nowick,et al.  Robust interfaces for mixed-timing systems with application to latency-insensitive protocols , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[6]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[7]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[8]  Jens Sparsø,et al.  The MANGO clockless network-on-chip: Concepts and implementation , 2006 .

[9]  Qiang Liu,et al.  IP Protection of Mesh NoCs Using Square Spiral Routing , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Rabi N. Mahapatra,et al.  Interfacing cores with on-chip packet-switched networks , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[11]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[12]  Ney Laert Vilar Calazans,et al.  MAIA - a framework for networks on chip generation and verification , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..