Minflotransit: min-cost flow based transistor sizing tool

This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool that has two alternating phases. For a circuit with |<italic>V</italic>| transistors and |<italic>E</italic>| wires, the first phase <italic>(D-phase)</italic>) is based on minimum cost network flow, which in our application, has a worst-case complexity of <italic>O</italic>(|<italic>V</italic>||<italic>E</italic>|<italic>log</italic>(<italic>log</italic>(|<italic>V</italic>|))). The second phase <italic>W-phase</italic> has a worst case complexity of <italic>O</italic>(|<italic>V</italic>||<italic>E</italic>|). In practice, during our simulations both the <italic>D-phase</italic> and <italic>W-phase</italic> show a near linear run-time dependence on the size of the circuit, comparable to TILOS. Simulation results show excellent run-time behavior for MINFLOTRANSIT on all the ISCAS85 benchmark circuits. For reasonable delay targets MINFLOTRANSIT shows up to 16.5% area savings over a circuit sized using a TILOS-like algorithm.

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