A novel floating-gate multiple-valued CMOS full-adder

In this paper we present a novel floating-gate (FG) multiple-valued (MV) CMOS adder. With the MV adder we can reduce the number of transistors required for adding two signals with a specific resolution. Furthermore, the MV adder is low-power due to the reduced number of transistors and the delay through a ripple adder can be reduced compared to conventional binary logic due to the reduced number of gates for the carry propagation. A binary to MV converter and a MV to binary converter are presented. Simulation data are obtained using the spectreS simulator. The chip has been sent for fabrication and measurements will be provided at the conference.