The Modeling and Design of Multiple Function-Unit Processors

A quantitative and systematic design procedure for multiple function-unit (MFU) processors and microprocessors is presented in this paper. The MFU organization employs a set of function units such as adders, multipliers, etc. to concurrently execute instructions from a single instruction stream. A set of parameters describing this processor organization and the programs it executes are presented. The instruction execution rate is used as the measure of performance. This can be defined as the number of instructions executed per unit time. An analytic model is presented which relates the performance of a processor to the parameters describing it. A general problem is formulated: ``Construct a processor that is optimal with respect to a certain design criterion.'' Two design criteria, which specify two design problems, are presented. The minimum cost (MC) problem specifies an optimal processor as one with a minimum cost while maintaining a minimal acceptable performance level. The maximum performance-to-cost ratio (MPCR) problem requires that the performance-to-cost ratio be maximized for the optimal processor. The design problem is formulated as an integer nonlinear programming problem. The branch and bound technique and other considerations are introduced to reduce the extent and amount of enumerations required. Illustrative examples are provided.