Formal Methods in Automated Design Debugging
暂无分享,去创建一个
[1] Helmut Veith,et al. Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis , 2002, FMCAD.
[2] Vamsi Boppana,et al. Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[3] Shi-Yu Huang,et al. Formal Equivalence Checking and Design Debugging , 1998 .
[4] Kwang-Ting Cheng,et al. Generation of shorter sequences for high resolution error diagnosis using sequential SAT , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[5] Marco Benedetti,et al. A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test , 2007, ICCAD 2007.
[6] Igor L. Markov,et al. Simulation-based bug trace minimization with BMC-based refinement , 2005, ICCAD 2005.
[7] Tracy Larrabee,et al. Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] P. R. Menon,et al. Critical Path Tracing: An Alternative to Fault Simulation , 1984, IEEE Des. Test.
[9] C. Y. Lee. Representation of switching circuits by binary-decision programs , 1959 .
[10] Edmund M. Clarke,et al. Sequential circuit verification using symbolic model checking , 1991, DAC '90.
[11] Roberto Bruttomesso,et al. The MathSAT 4 SMT Solver ( Tool Paper ) , 2008 .
[12] G. S. Tseitin. On the Complexity of Derivation in Propositional Calculus , 1983 .
[13] Himanshu Bhatnagar. Advanced ASIC Chip Synthesis: Using Synopsys' Design Compiler and PrimeTime , 1999 .
[14] Sean Safarpour,et al. Improved Design Debugging Using Maximum Satisfiability , 2007 .
[15] Fabio Somenzi,et al. Efficient manipulation of decision diagrams , 2001, International Journal on Software Tools for Technology Transfer.
[16] Niklas Sörensson,et al. An Extensible SAT-solver , 2003, SAT.
[17] Per Bjesse,et al. Using counter example guided abstraction refinement to find complex bugs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[18] Daniel Kroening,et al. Word level predicate abstraction and refinement for verifying RTL Verilog , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[19] Karem A. Sakallah,et al. Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints , 2007, Journal of Automated Reasoning.
[20] Rolf Drechsler,et al. Post-verification debugging of hierarchical designs , 2005, ICCAD 2005.
[21] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[22] Ying Qin,et al. A faster counterexample minimization algorithm based on refutation analysis , 2005, Design, Automation and Test in Europe.
[23] Janick Bergeron,et al. Writing Testbenches: Functional Verification of HDL Models , 2000 .
[24] Shi-Yu Huang. A fading algorithm for sequential fault diagnosis [logic IC testing] , 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..
[25] Bin Li,et al. A novel SAT all-solutions solver for efficient preimage computation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[26] Farzan Fallah. Coverage-directed validation of hardware models , 1999 .
[27] Mache Creeger,et al. Evolution or Revolution? , 2006, ACM Queue.
[28] Thomas Kropf,et al. Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.
[29] Shi-Yu Huang,et al. ErrorTracer: design error diagnosis based on fault simulation techniques , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[30] Igor L. Markov,et al. Automating Postsilicon Debugging and Repair , 2007, Computer.
[31] Christopher Lynch,et al. Interpolants for Linear Arithmetic in SMT , 2008, ATVA.
[32] Donald W. Loveland,et al. A machine program for theorem-proving , 2011, CACM.
[33] Sean Safarpour,et al. Efficient SAT-based Boolean matching for FPGA technology mapping , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[34] Karem A. Sakallah,et al. On Finding All Minimally Unsatisfiable Subformulas , 2005, SAT.
[35] Ofer Strichman,et al. Pruning Techniques for the SAT-Based Bounded Model Checking Problem , 2001, CHARME.
[36] Rolf Drechsler,et al. On the relation between simulation-based and SAT-based diagnosis , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[37] Hassen Saïdi,et al. Construction of Abstract State Graphs with PVS , 1997, CAV.
[38] Luciano Lavagno,et al. EDA for IC Implementation, Circuit Design, and ProcessTechnology (Electronic Design Automation for Integrated Circuits Handbook) , 2006 .
[39] W. Kunz,et al. Record and play: a structural fixed point iteration for sequential circuit verification , 1997, ICCAD 1997.
[40] Rolf Drechsler,et al. Integrating observability don't cares in all-solution SAT solvers , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[41] Sean Safarpour,et al. Abstraction and refinement techniques in automated design debugging , 2007 .
[42] Andreas G. Veneris,et al. Incremental fault diagnosis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[43] Ibrahim N. Hajj,et al. Design error diagnosis and correction via test vector simulation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[44] Albert Oliveras,et al. MiniMaxSat: A New Weighted Max-SAT Solver , 2007, SAT.
[45] In-Cheol Park,et al. SAT-based unbounded symbolic model checking , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[46] Malay K. Ganai,et al. Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[47] Sean Safarpour,et al. Trace Compaction using SAT-based Reachability Analysis , 2007, 2007 Asia and South Pacific Design Automation Conference.
[48] Yirng-An Chen,et al. Algorithms for compacting error traces , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..
[49] R. K. Shyamasundar,et al. Introduction to algorithms , 1996 .
[50] Helmut Veith,et al. Counterexample-guided abstraction refinement for symbolic model checking , 2003, JACM.
[51] Harry D. Foster,et al. Assertion-Based Design , 2010 .
[52] Edmund M. Clarke. SAT-Based Counterexample Guided Abstraction Refinement , 2002, SPIN.
[53] Andreas Veneris,et al. A succinct memory model for automated design debugging , 2008, ICCAD 2008.
[54] Qi Zhu,et al. SAT sweeping with local observability don't-cares , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[55] Stephen A. Cook,et al. The complexity of theorem-proving procedures , 1971, STOC.
[56] Andreas G. Veneris,et al. Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability , 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[57] Andreas G. Veneris,et al. Automated data analysis solutions to silicon debug , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[58] Leendert M. Huisman. Diagnosing arbitrary defects in logic designs using single location at a time (SLAT) , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[59] Andreas G. Veneris,et al. Design rewiring using ATPG , 2002, Proceedings. International Test Conference.
[60] Andreas Veneris,et al. Design diagnosis using Boolean satisfiability , 2004 .
[61] Edward A. Hirsch,et al. SAT Local Search Algorithms: Worst-Case Study , 2000, Journal of Automated Reasoning.
[62] Joao Marques-Silva,et al. Algorithms for Maximum Satisfiability using Unsatisfiable Cores , 2008, 2008 Design, Automation and Test in Europe.
[63] Rolf Drechsler,et al. Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment , 2002 .
[64] Niraj K. Jha,et al. Testing of Digital Systems , 2003 .
[65] Rolf Drechsler,et al. Debugging sequential circuits using Boolean satisfiability , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[66] Karem A. Sakallah,et al. GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.
[67] Ofer Shtrichman. Pruning Techniques for the SAT-Based Bounded Model Checking Problem , 2001 .
[68] Hilary Putnam,et al. A Computing Procedure for Quantification Theory , 1960, JACM.
[69] Rob A. Rutenbar,et al. A New FPGA Detailed Routing Approach Via , 2002 .
[70] Robert K. Brayton,et al. Using SAT for combinational equivalence checking , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[71] Armin Biere,et al. Bounded model checking , 2003, Adv. Comput..
[72] Joao Marques-Silva,et al. GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.
[73] Harry Foster,et al. Principles of verifiable RTL design , 2000 .
[74] Nachum Dershowitz,et al. Bounded Model Checking with QBF , 2005, SAT.
[75] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[76] Pei-Hsin Ho,et al. Abstraction refinement by controllability and cooperativeness analysis , 2004, Proceedings. 41st Design Automation Conference, 2004..
[77] J. P. Marques,et al. GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .
[78] Edmund M. Clarke,et al. Symbolic Model Checking with Partitioned Transistion Relations , 1991, VLSI.
[79] Sartaj Sahni,et al. The Complexity of Design Automation Problems , 1980, 17th Design Automation Conference.
[80] Weitong Chuang,et al. Circuit-level dictionaries of CMOS bridging faults , 1994, Proceedings of IEEE VLSI Test Symposium.
[81] Sharad Malik,et al. Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[82] David A. Plaisted,et al. A Structure-Preserving Clause Form Translation , 1986, J. Symb. Comput..
[83] Armin Biere,et al. Bounded Model Checking Using Satisfiability Solving , 2001, Formal Methods Syst. Des..
[84] Shi-Yu Huang,et al. A Fading Algorithm For Sequential Fault Diagnosis , 2004, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
[85] Rolf Drechsler,et al. Using unsatisfiable cores to debug multiple design errors , 2008, GLSVLSI '08.
[86] F. Ferrari,et al. System-on-a-chip verification~methodology and techniques , 2002, IEEE Circuits and Devices Magazine.
[87] Per Bjesse,et al. DAG-aware circuit compression for formal verification , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[88] P. R. Stephan,et al. SIS : A System for Sequential Circuit Synthesis , 1992 .
[89] Sean Safarpour,et al. Automated Design Debugging With Abstraction and Refinement , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[90] Andreas G. Veneris. Fault diagnosis and logic debugging using Boolean satisfiability , 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.
[91] Rolf Drechsler,et al. Improved SAT-based Reachability Analysis with Observability Don't Cares , 2008, J. Satisf. Boolean Model. Comput..
[92] Kenneth L. McMillan,et al. Applying SAT Methods in Unbounded Symbolic Model Checking , 2002, CAV.
[93] Armin Biere,et al. Symbolic Model Checking without BDDs , 1999, TACAS.
[94] Kwang-Ting Cheng,et al. A circuit SAT solver with signal correlation guided learning , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.