FPGA-Based Research on The Hardware Design of CAVLC Encoder

H.264/AVC video coding standard adopt CAVLC (Context-based Adaptive Variable Length Coding) in Baseline profile and Extended profile, this paper briefly introduces the principle of CAVLC encoding; In the hardware design, the PingPong operation and structure of parallel processing are adopted in order to reduce CAVLC encoded clock cycle and improve the throughput. All hardware circuits are described by Verilog HDL, and are simulated by using Modelsim SE 6.5, and are verified by using ALTERA Cyclone II EP2C35F672C8 FPGA.