A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10-12 while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm2.

[1]  B. Razavi,et al.  Analysis and modeling of bang-bang clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[2]  Deog-Kyoon Jeong,et al.  A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[3]  Pervez M. Aziz,et al.  A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[4]  Pavan Kumar Hanumolu,et al.  Digital clock and data recovery circuit design: Challenges and tradeoffs , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[5]  Richard C. Walker,et al.  A two-chip 1.5-GBd serial link interface , 1992 .

[6]  Jeff Sanders,et al.  A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications , 2012, 2012 IEEE International Solid-State Circuits Conference.

[7]  Yoichi Koyanagi,et al.  An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS , 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[8]  Pervez M. Aziz,et al.  A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[9]  Deog-Kyoon Jeong,et al.  A Fully Integrated 0.13- $\mu$m CMOS 40-Gb/s Serial Link Transceiver , 2009, IEEE Journal of Solid-State Circuits.

[10]  Steve Howard,et al.  AC-coupling strategy for high-speed transceivers of 10Gbps and beyond , 2007, 2007 IFIP International Conference on Very Large Scale Integration.

[11]  Mounir Meghelli,et al.  A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology , 2013 .

[12]  Mounir Meghelli,et al.  A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[13]  Pedro Reviriego,et al.  IEEE 802.3az: the road to energy efficient ethernet , 2010, IEEE Communications Magazine.

[14]  W. Walker,et al.  A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[15]  S. Gowda,et al.  A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[16]  Jaeha Kim,et al.  Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Deog-Kyoon Jeong,et al.  Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Thomas Toifl,et al.  A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology , 2012, IEEE Journal of Solid-State Circuits.

[19]  S. Hale,et al.  A 5.2Gbps hypertransportTM integrated AC coupled receiver with DFR DC restore , 2007, 2007 IEEE Symposium on VLSI Circuits.