On Hard Adders and Carry Chains in FPGAs

Hardened adder and carry logic is widely used in commercial FPGAs to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the CAD flow. There has been very little study, however, on these choices and hence we explore a number of possibilities for hard adder design. We also highlight optimizations during front-end elaboration that help ameliorate the restrictions placed on logic synthesis by hardened arithmetic. We show that hard adders and carry chains, when used for simple adders, increase performance by a factor of four or more, but on larger benchmark designs that contain arithmetic, improve overall performance by roughly 15%. We measure an average area increase of 5% for architectures with carry chains but believe that better logic synthesis should reduce this penalty. Interestingly, we show that adding dedicated inter-logic-block carry links or fast carry look-ahead hardened adders result in only minor delay improvements for complete designs.

[1]  Scott Hauck,et al.  High-performance carry chains for FPGA's , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Vaughn Betz,et al.  COFFE: Fully-automated transistor sizing for FPGAs , 2013, 2013 International Conference on Field-Programmable Technology (FPT).

[3]  Shanzhen Xing,et al.  FPGA Adders: Performance Evaluation and Optimal Design , 1998, IEEE Des. Test Comput..

[4]  Jonathan Rose,et al.  Area and delay trade-offs in the circuit and architecture design of FPGAs , 2008, FPGA '08.

[5]  Jason Luu,et al.  Towards interconnect-adaptive packing for FPGAs , 2014, FPGA.

[6]  David M. Lewis,et al.  Architectural enhancements in Stratix V™ , 2013, FPGA '13.

[7]  Kenneth B. Kent,et al.  The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.

[8]  Fei Li,et al.  A 65nm flash-based FPGA fabric optimized for low cost and power , 2011, FPGA '11.

[9]  Jonathan Rose,et al.  Hard vs. soft: the central question of pre-fabricated silicon , 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

[10]  Nam Sung Woo,et al.  Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[11]  Paolo Ienne,et al.  A novel FPGA logic block for improved arithmetic performance , 2008, FPGA '08.

[12]  Paolo Ienne,et al.  Efficient synthesis of compressor trees on FPGAs , 2008, 2008 Asia and South Pacific Design Automation Conference.

[13]  Vaughn Betz,et al.  Titan: Enabling large and complex benchmarks in academic CAD , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[14]  William S. Carter,et al.  Third-generation architecture boosts speed and density of field-programmable gate arrays , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[15]  HauckScott,et al.  High-performance carry chains for FPGA's , 2000 .

[16]  Robert K. Brayton,et al.  SmartOpt: an industrial strength framework for logic synthesis , 2009, FPGA '09.