A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 $\mu$m CMOS
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[1] Amr Elshazly,et al. A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC , 2012, 2012 IEEE International Solid-State Circuits Conference.
[2] Shin-Il Lim,et al. Charge pump with perfect current matching characteristics in phase-locked loops , 2000 .
[3] William J. Dally,et al. A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips , 2002, IEEE J. Solid State Circuits.
[4] Giovanni Marzin,et al. A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power , 2011, 2011 IEEE International Solid-State Circuits Conference.
[5] SeongHwan Cho,et al. A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).
[6] Sheng Ye,et al. A multiple-crystal interface PLL with VCO realignment to reduce phase noise , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[7] Pui Ying Or,et al. An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection , 2010, IEEE Journal of Solid-State Circuits.
[8] B. Helal,et al. A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop , 2008, IEEE Journal of Solid-State Circuits.
[9] Lars C. Jansson,et al. A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation , 2004, IEEE Journal of Solid-State Circuits.
[10] Bram Nauta,et al. A 2.2GHz sub-sampling PLL with 0.16psrms jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power , 2010, 2010 Symposium on VLSI Circuits.
[11] Matthew Z. Straayer,et al. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.
[12] Ali Afzali-Kusha,et al. Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications , 2005 .
[13] SeongHwan Cho,et al. A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.
[14] S.L.J. Gierkink,et al. Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump , 2008, IEEE Journal of Solid-State Circuits.
[15] Shen-Iuan Liu,et al. A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing , 2012, 2012 IEEE International Solid-State Circuits Conference.
[16] Che-Fu Liang,et al. An injection-locked ring PLL with self-aligned injection window , 2011, 2011 IEEE International Solid-State Circuits Conference.
[17] Eric A. M. Klumperink,et al. Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[18] Ron Ho,et al. A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning , 2011, 2011 IEEE International Solid-State Circuits Conference.