Imaging Latch-up Sites in CMOS Integrated Circuits Using Laser Scanning

A novel approach to using laser scanning to analyze latch-up sites in complementary metal-oxide semiconductor (CMOS) integrated circuits (IC's) has been developed. The technique employs a continuous wave (CW) laser beam scanned across a CMOS IC as the power to the IC is modulated. Signals corresponding to latch-up currents are detected with a lock-in amplifier and are used to produce a two-dimensional image of latch-up sites on a high resolution monitor.

[1]  G. Derbenwick,et al.  Prevention of CMOS Latch-Up by Gold Doping , 1976, IEEE Transactions on Nuclear Science.

[2]  F. J. Henley,et al.  CMOS Latch-Up Characterization using a Laser Scanner , 1983, 21st International Reliability Physics Symposium.

[3]  John Hiatt,et al.  A Method of Detecting Hot Spots on Semiconductors using Liquid Crystals , 1981, 19th International Reliability Physics Symposium.

[4]  A. Ochoa,et al.  Latch-Up Control in CMOS Integrated Circuits , 1979, IEEE Transactions on Nuclear Science.

[5]  R. J. Sokel,et al.  Neutron Irradiation for Prevention of Latch-Up in MOS Integrated Circuits , 1979, IEEE Transactions on Nuclear Science.

[6]  S M Davidson,et al.  Latch-Up and Timing Failure Analysis of CMOS VLSI using Electron Beam Techniques , 1983, 21st International Reliability Physics Symposium.

[7]  A. Ochoa,et al.  Latch-Up Elimination in Bulk CMOS LSI Circuits , 1980, IEEE Transactions on Nuclear Science.

[8]  Daniel J. Burns,et al.  Imaging Latch-Up Sites in LSI CMOS with a Laser Photoscanner , 1983, 21st International Reliability Physics Symposium.