Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT

This paper presents new DSP (digital signal processor) instructions and their hardware architecture for high-speed FFT. The instructions perform new operation flows, which are different from the MAC (multiply and accumulate) operation on which existing DSP chips heavily depend. The paper proposes a DPU (data processing unit) supporting the instructions and shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 /spl mu/m standard cell library. The maximum operating clock frequency is about 144.5 MHz and the architecture will be employed on an application-specific DSP chip.