A GaAs 32-bit adder

Presents a new parallel GaAs 32-bit adder based on a combination of the Han-Carlson (1987) and Kowalczuk (1991) parallel adders. GaAs is particularly sensitive to loading, so our aim was to reduce the wire lengths and the fanout of each gate. Our architecture achieves this by significantly reducing the number of cells in the carry tree while not significantly reducing its speed. The delay of the adder fabricated in 0.6 /spl mu/m MESFET GaAs technology was measured at 1.27 ns, with a power dissipation of 114 mW at 0.9 V. The area is 0.3 mm/sup 2/ with a maximum density of 8000 transistors/mm/sup 2/. The figure of merit is 0.21 /spl mu/W/MHz/spl middot/gate.

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