Modes of failure of MOS devices

Abstract A review is presented of the physical basis of loss of yield and failure of integrated circuits containing MOS devices. The causes of variations in both threshold voltage and other parameters are described. The effects of oxide and silicon defects on chip yield and reliability are discussed. Also included is a diagnostic table summarizing the means of distinguishing between the various modes of failure. All the physical effects are described with reference to p -channel aluminium gate devices. Extension of the results to other forms of MOS device should in most cases be obvious, as should the recognition of the phenomena on capacitance-voltage curves.

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