On the fast computation of decimal logarithm

The paper presents a new and fast algorithm to efficiently compute radix-10 logarithm of a decimal number. The algorithm uses 32-bit floating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations; the number of iterations depends on the user defined precision. The algorithm produces error-free (infinite precision) results up to 7 decimal digits. A numerical example is shown for the purpose of illustration. The accuracy is analyzed for several decimal digits showing compliance with the IEEE 754-2008 standard. When implemented on to the Xilinx VirtexII FPGA, the architecture costs only 1,053 logic cells, runs at a maximum frequency of 44 MHz, and consumes 79 mW of power.

[1]  Hao-Yung Lo,et al.  A Hardwired Generalized Algorithm for Generating the Logarithm Base-k by Iteration , 1987, IEEE Transactions on Computers.

[2]  Li Chen,et al.  A novel decimal-to-decimal logarithmic converter , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[3]  Demetrios K. Kostopoulos,et al.  An Algorithm for the Computation of Binary Logarithms , 1991, IEEE Trans. Computers.

[4]  Yu Zhang,et al.  A 32-bit Decimal Floating-Point Logarithmic Converter , 2009, 2009 19th IEEE Symposium on Computer Arithmetic.

[5]  Milos D. Ercegovac.  Radix-16 Evaluation of Certain Elementary Functions , 1973, IEEE Transactions on Computers.

[6]  Ping Tak Peter Tang.  Table-driven implementation of the logarithm function in IEEE floating-point arithmetic , 1990, TOMS.

[7]  Florent de Dinechin,et al.  Return of the hardware floating-point elementary function , 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

[8]  A. Nannarelli,et al.  A Radix-10 Combinational Multiplier , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[9]  E. V. Krishnamurthy,et al.  On Computer Multiplication and Division Using Binary Logarithms , 1963, IEEE Transactions on Electronic Computers.

[10]  Mário P. Véstias,et al.  Decimal multiplier on FPGA using embedded binary multipliers , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[11]  Tien Chi Chen,et al.  Convergence guarantee and improvements for a fast hardware exponential and logarithm evaluation scheme , 1978, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH).

[12]  Michael F. Cowlishaw,et al.  Decimal floating-point: algorism for computers , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[13]  Weng-Fai Wong,et al.  Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers , 1994, IEEE Trans. Computers.

[14]  James Demmel,et al.  IEEE Standard for Floating-Point Arithmetic , 2008 .

[15]  F. de Dinechin,et al.  A parameterizable floating-point logarithm operator for FPGAs , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..