Novel Addressing Method for Aggregate Types in Queue Processors

Queue processors use a first-in first-out data structure to perform operations. Instructions implicitly reference their operands simplifying the design of the instruction set and the hardware complexity. Some access to memory require a computed address. A register-indirect addressing method introduces severe limitations in a queue processor by inserting false dependencies that limit the high parallelism capacity of such architectures. In this paper we propose a novel addressing method for queue processors that employ the queue for address calculation and memory access. We demonstrate that our new proposed method reduces the number of instructions by 6% and increases parallelism by 4% for a set of embedded applications.

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