Design of an efficient shared memory architecture using hybrid opto-electronic VLSI circuits and space invariant optical buses

We present a shared memory (SM) parallel computer architecture designed to take advantage of the integration of a large number of optical I/Os on VLSI circuits. It is shown how the unique features of this new technology can be exploited to build a high performance, uniform memory access SM scalable to up to 1000 processors. Our architecture relies on a space invariant broadcast topology that can be easily implemented using fiber arrays or simple robust free space opto-mechanics. The paper presents the concept of the architecture and describes the design of the components and protocols needed for its implementation.

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