A 0.1–5GHz flexible SDR receiver in 65nm CMOS

A 0.1-5GHz flexible software-defined radio (SDR) receiver is presented with three RF front-end paths (Main/Sub/HR paths). Main path and sub path can reject out-of-band blockers and harmonic interferences, and feature low NF and high linearity, respectively. Harmonic rejection (HR) path can effectively reject the harmonic interferences with simple calibration mechanism. Dual feedback LNA, class-AB Op-Amp with miller feed-forward compensation and quasi-floating gate (QFG) techniques, reconfigurable continuous-time (CT) low pass (LP) and complex band pass (CBP) sigma-delta ADC are proposed. This chip has been implemented in 65nm CMOS with 9.6-47.4mA current consumption from 1.2V voltage supply and a core chip area of 5.4mm2. The receiver main path achieves 3.8dB NF, +5dBm/+5dBm IB-IIP3/OB-IIP3 as well as +58dBm IIP2. The sub path achieves +10dBm/+18dBm IB-IIP3/OB-IIP3 as well as +61dBm IIP2. And it offers RF filtering with 10dB rejection at 10MHz offset. The HR path achieves +13dBm/+14dBm IB-IIP3/OB-IIP3 and >54/56dB 3rd/5th-order harmonic rejection with 30-40dB rejection improvement by calibration.

[1]  Rinaldo Castello,et al.  SAW-less analog front-end receivers for TDD and FDD , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Minjae Lee,et al.  An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[3]  Jonathan Borremans,et al.  A 0.9V low-power 0.4–6GHz linear SDR receiver in 28nm CMOS , 2013, 2013 Symposium on VLSI Circuits.

[4]  Serge Toutain,et al.  A 60 dB Harmonic Rejection Mixer for Digital Terrestrial TV Tuner , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  A.J. Lopez-Martin,et al.  Very low-voltage analog signal processing based on quasi-floating gate transistors , 2004, IEEE Journal of Solid-State Circuits.

[6]  Alyosha C. Molnar,et al.  A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface , 2010, IEEE Journal of Solid-State Circuits.

[7]  Jonathan Borremans,et al.  A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers , 2011, 2011 IEEE International Solid-State Circuits Conference.

[8]  Ahmad Mirzaei,et al.  A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure , 2012, 2012 IEEE International Solid-State Circuits Conference.