Polymorphic Gates in Design and Test of Digital Circuits

A rolling-bearing-mounted linear guiding unit comprising a hardened and polished guide rail on which rolling element raceways are formed and a guide carriage longitudinally displaceably mounted on the guide rail and provided with a fixing surface turned away from the guide rail and an inner contour adapted in shape to the profile of the guide rail, rolling elements rolling in endless race canals between the rolling element raceways of the guide rail and surfaces situated opposite to these in the guide carriage and a damping element bveing provided next to the guide carriage and a damping element being provided next to the guide carriage and forming a damping gap with the guide rail, characterized in that the damping element is formed as a saddle engaging around the guide rail, which saddle in respect of the guide rail, has a fixing surface identical to that of the guide carriage, the inner contour of the saddle being adapted for the most part to the profile of the guide rail so that these delimit a damping gap of 0 to 40 mu m.

[1]  Julian Francis Miller,et al.  Principles in the Evolutionary Design of Digital Circuits—Part II , 2000, Genetic Programming and Evolvable Machines.

[2]  Donald E. Knuth,et al.  The art of computer programming: sorting and searching (volume 3) , 1973 .

[3]  Zdenek Kotásek,et al.  Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[4]  Irith Pomeranz,et al.  Static test compaction for multiple full-scan circuits , 2003, Proceedings 21st International Conference on Computer Design.

[5]  W S McCulloch,et al.  A logical calculus of the ideas immanent in nervous activity , 1990, The Philosophy of Artificial Intelligence.

[6]  Adrian Stoica,et al.  Polymorphic Electronics , 2001, ICES.

[7]  Janak H. Patel,et al.  Partial scan design based on circuit state information and functional analysis , 2004, IEEE Transactions on Computers.

[8]  Lukás Sekanina,et al.  Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[9]  Adrian Stoica,et al.  Three-Function Logic Gate Controlled by Analog Voltage , 2006 .

[10]  Julian Francis Miller,et al.  Towards the automatic design of more efficient digital circuits , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[11]  Xin Guo,et al.  Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration , 2004 .

[12]  Donald E. Knuth,et al.  The Art of Computer Programming: Volume 3: Sorting and Searching , 1998 .

[13]  Priyank Kalla,et al.  A comprehensive approach to the partial scan problem using implicit state enumeration , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  Lukás Sekanina,et al.  Evolutionary Design of Gate-Level Polymorphic Digital Circuits , 2005, EvoWorkshops.

[15]  R. Brooks The relationship between matter and life , 2001, Nature.

[16]  Sungju Park,et al.  A partial scan design by unifying structural analysis and testabilities , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[17]  Aristides Efthymiou,et al.  Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Grzegorz Rozenberg,et al.  Nanotechnology: Science and Computation , 2006, Nanotechnology: Science and Computation.

[19]  Priyank Kalla,et al.  A comprehensive approach to the partial scan problem using implicitstate enumeration , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Mark A. Ratner,et al.  Molecular electronics , 2005 .

[21]  Adrian Stoica,et al.  On Polymorphic Circuits and Their Design Using Evolutionary Algorithms , 2002 .

[22]  Wen-Ben Jone,et al.  Fault simulation and response compaction in full scan circuits using HOPE , 2005, IEEE Transactions on Instrumentation and Measurement.

[23]  André DeHon,et al.  Seven strategies for tolerating highly defective fabrication , 2005, IEEE Design & Test of Computers.