An ON-resistance closed form for VDMOS devices

An analytical ON-resistance expression for different designs of VDMOS (vertically diffused metal-oxide-semiconductor) devices which takes into consideration the two-dimensional (2-D) nature of the current flow is obtained. This expression differs from other models that overestimate this resistance for large cell spacings. This formulation is in close agreement with experimental points obtained from the interdigitated fabricated structures and with 2-D simulations. Moreover, the effect of a two-level oxide thickness on the ON resistance has been investigated for the interdigitated case.<<ETX>>

[1]  A. Papoulis BAMBI-A Design Model for Power MOSFET's , 1985 .

[2]  J.D. Plummer,et al.  Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors , 1980, IEEE Transactions on Electron Devices.

[3]  D. Ueda,et al.  A new vertical double diffused MOSFET—The self-aligned terraced-gate MOSFET , 1984, IEEE Transactions on Electron Devices.

[4]  K. Board,et al.  The optimization of on-resistance in vertical DMOS power devices with linear and hexagonal surface geometries , 1984, IEEE Transactions on Electron Devices.

[5]  P. Hower,et al.  Comparison of various source-gate geometries for power MOSFET's , 1981, IEEE Transactions on Electron Devices.

[6]  Chenming Hu,et al.  Optimum design of power MOSFET's , 1984, IEEE Transactions on Electron Devices.