One of the primary goals of computer architects is to design computers that are more costeffective than their predecessors. Cost-effectiveness includes the cost of hardware to manufacture the machine, the cost of programming, and costs incurred related to the architecture in debugging both the initial hardware and subsequent programs. If we review the history of computer families we find that the most common architectural change is the trend toward ever more complex machines. Presumably this additional complexity has a positive tradeoff with regard to the costeffectiveness of newer models. In this paper we propose that this trend is not always cost-effective, and in fact, may even do more harm than good. We shall examine the case for a Reduced Instruction Set Computer (RISC) being as cost-effective as a Complex Instruction Set Computer (CISC). This paper will argue that the next generation of VLSI computers may be more effectively implemented as RISC's than CISC's.
[1]
Edward M. Riseman,et al.
Measures of Op-Code Utilization
,
1971,
IEEE Transactions on Computers.
[2]
Stephen C. Johnson.
A 32-bit processor design
,
1979
.
[3]
David B. Wortman,et al.
Static and Dynamic Characteristics of XPL Programs
,
1975,
Computer.
[4]
Leonard Jay Shustek,et al.
Analysis and performance of computer instruction sets
,
1978
.
[5]
Carlo H. Séquin,et al.
Design Considerations for Single-Chip Computers of the Future
,
1980
.
[6]
David A. Patterson,et al.
Retrospective on High-Level Language Computer Architecture
,
1980,
ISCA.
[7]
Samir S. Husson,et al.
Microprogramming: principles and practices
,
1971,
SIGM.
[8]
Leonard J. Shustek,et al.
An instruction timing model of CPU performance
,
1977,
ISCA '77.