An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple-material double-gate DG metal-oxide-semiconductor field-effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple-material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short-channel effects is evaluated by comparing the relative performance parameters such as drain-induced barrier lowering, threshold voltage roll-off, and subthreshold swing with its counterparts in the single-material DG and double-material DG metal-oxide-semiconductor field-effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate-engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum-mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.

[1]  S. Baishya,et al.  A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions , 2006, IEEE Transactions on Electron Devices.

[2]  Satyabrata Jit,et al.  A two-dimensional analytical model for threshold voltage of short-channel triple-material double-gate metal-oxide-semiconductor field-effect transistors , 2010 .

[3]  Subhasis Haldar,et al.  Physics-based modelling and simulation of dual material gate stack (DUMGAS) MOSFET , 2003 .

[4]  H.-S.P. Wong,et al.  Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[5]  Chandan Kumar Sarkar,et al.  Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model , 2012 .

[6]  Mei-Li Chen,et al.  A New Two-Dimensional Analytical Model for Nanoscale Symmetrical Tri-Material Gate Stack Double Gate Metal–Oxide–Semiconductor Field Effect Transistors , 2009 .

[7]  M.J. Kumar,et al.  Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs , 2004, IEEE Transactions on Electron Devices.

[8]  K. Chin,et al.  Dual material gate field effect transistor (DMGFET) , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[9]  T. Ouisse,et al.  Ultimately thin double-gate SOI MOSFETs , 2003 .

[10]  Amara Amara,et al.  Planar Double-Gate Transistor: From technology to circuit , 2009 .

[11]  V. Trivedi,et al.  Pragmatic design of nanoscale multi-gate CMOS , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[12]  Chandan Kumar Sarkar,et al.  Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs , 2007 .

[13]  C.K. Sarkar,et al.  A Pseudo Two-Dimensional Subthreshold Surface Potential Model for Dual-Material Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.

[14]  Chandan Kumar Sarkar,et al.  Effect of gate engineering in double-gate MOSFETs for analog/RF applications , 2012, Microelectron. J..

[15]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[16]  A. Orouji,et al.  Nanoscale Triple Material Double Gate (TM-DG) MOSFET for Improving Short Channel Effects , 2008, 2008 International Conference on Advances in Electronics and Micro-electronics.

[17]  Ian O'Connor,et al.  Analog Circuit Design (chapter 5) , 2009 .

[18]  Te-Kuang Chiang A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET's , 2009, Microelectron. Reliab..

[19]  D. Munteanu,et al.  Quantum short-channel compact modeling of drain-current in double-gate MOSFET , 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

[20]  J. H. Davies,et al.  The physics of low-dimensional semiconductors , 1997 .

[21]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[22]  V. Misra,et al.  Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS , 2003, IEEE International Electron Devices Meeting 2003.

[23]  Chandan Kumar Sarkar,et al.  1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model , 2012, IET Circuits Devices Syst..

[24]  K. Goel,et al.  Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects , 2006, IEEE Transactions on Electron Devices.

[25]  Yuan Taur,et al.  Compact modeling of quantum effects in symmetric double-gate MOSFETs , 2010, Microelectron. J..

[26]  Chenming Hu,et al.  Dual work function metal gate CMOS technology using metal interdiffusion , 2001, IEEE Electron Device Letters.

[27]  Yeong-Seuk Kim,et al.  Silicon Complementary Metal–Oxide–Semiconductor Field-Effect Transistors with Dual Work Function Gate , 2006 .

[28]  G. V. Reddy,et al.  Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs – A two-dimensional analytical approach , 2004 .

[29]  Satyabrata Jit,et al.  Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs , 2012 .

[30]  V. Trivedi,et al.  Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs , 2005, IEEE Electron Device Letters.

[31]  Chandan Kumar Sarkar,et al.  A new analytical subthreshold model of SRG MOSFET with analogue performance investigation , 2012 .

[32]  J. A. Ott,et al.  Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[33]  Mamidala Jagadesh Kumar,et al.  Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study , 2004, Microelectron. J..

[34]  X. Garros,et al.  75 nm damascene metal gate and high-k integration for advanced CMOS devices , 2002, Digest. International Electron Devices Meeting,.

[35]  D. Kwong,et al.  A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate , 2004, IEEE Electron Device Letters.

[36]  G. Gildenblat,et al.  PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation , 2006, IEEE Transactions on Electron Devices.

[37]  Husam N. Alshareef,et al.  Integration of dual metal gate CMOS on high-k dielectrics utilizing a metal wet etch process , 2005 .

[38]  P. Suveetha Dhanaselvam,et al.  Analytical approach of a nanoscale triple-material surrounding gate (TMSG) MOSFETs for reduced short-channel effects , 2013, Microelectron. J..

[39]  M.J. Kumar,et al.  A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation , 2005, IEEE Transactions on Nanotechnology.

[40]  A. Sarkar,et al.  Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling , 2013 .

[41]  Santanu Mahapatra,et al.  Analytical modeling of quantum threshold voltage for triple gate MOSFET , 2010 .

[42]  Sean Wu,et al.  A New Two-Dimensional Analytical Threshold Voltage Model for Short-Channel Triple-Material Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors , 2012 .

[43]  J. Liu,et al.  Dual-work-function metal gates by full silicidation of poly-Si with Co-Ni bi-Layers , 2005, IEEE Electron Device Letters.

[44]  M. Gupta,et al.  TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET , 2011, IEEE Transactions on Electron Devices.

[45]  S. Mahapatra,et al.  Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor , 2011, IEEE Transactions on Nanotechnology.