Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET

SRAM SER measurements across technology nodes indicate that while scaling from planar processes down to the 7-nm FinFET process provided a reduction in the per-bit SER at every node, subsequent scaling to the 5-nm FinFET process results in an increase in the per-bit SER relative to the 7-nm FinFET process. Extensive data collected across a range of supply voltages show strong exponential bias dependence of SRAM SER for FinFET processes, but the rate of increase in SER as supply voltage is reduced is lower for the 5-nm process compared to the 7-nm. Simulations and modeling indicate that variations in the critical charge ($Q_{crit}$) is the key reason for the observed trends.