论文信息 - Silicon c: a hardware backend for suif

Silicon c: a hardware backend for suif

High-level languages have much to offer the hardware designer. Freed of the tyranny of gates, it is possible to approach circuit function in terms of the algorithm or protocol it implements. Design rule checking and gate-level optimizations are becoming impossible for large designs without computer assistance anyway, the argument goes, so why not delegate all low-level design and synthesis to the machine, and free the humans to work on the high-level tasks the machine is incapable of?

C. Scott Ananian | C. Ananian

[1] Andrew Rushton. VHDL for Logic Synthesis: An Introductory Guide for Achieving Design Requirements , 1995 .

[2] Mark N. Wegman,et al. Efficiently computing static single assignment form and the control dependence graph , 1991, TOPL.

[3] Eduardo Sanchez,et al. A C++ compiler for FPGA custom execution units synthesis , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[4] Georg Sander,et al. Graph Layout through the VCG Tool , 1994, GD.

[5] Lennart Lindh,et al. VHDL For Designers , 1997 .

[6] Steve Golson,et al. State Machine Design Techniques for Verilog and VHDL , 1998 .

[7] Donald E. Thomas,et al. The Verilog® Hardware Description Language , 1990 .

[8] Steven W. K. Tjiang,et al. SUIF: an infrastructure for research on parallelizing and optimizing compilers , 1994, SIGP.

[9] Andrew W. Appel,et al. Modern Compiler Implementation in Java , 1997 .

[10] Peter M. Athanas,et al. Quantitative analysis of floating point arithmetic on FPGA based custom computing machines , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[11] David R. Galloway. The Transmogrifier C hardware description language and compiler for FPGAs , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[12] Maya Gokhale,et al. Data-parallel C on a reconfigurable logic array , 2005, The Journal of Supercomputing.