Production planning in semiconductor assembly

The semiconductor manufacturing process usually consists of four main production stages: wafer fabrication, probe, assembly, and final test. This paper considers the lot-sizing and scheduling problem in the assembly stages. A hierarchical solution approach is outlined with focus on the first of three suggested phases, namely the bottleneck lot-sizing and scheduling phase. The approach integrates back-ordering, setup carry-over and parallel machines. A single-stage lot-sizing and scheduling problem on the bottleneck stage on product family level is solved using a new solution procedure. Core of the solution procedure is a new mixed integer programming (MIP) model that works with integer instead of binary variables. The model is embedded in a period-by-period heuristic to generate a solution to the original problem.

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