Understanding and Analyzing the Impact of Memory Controller's Scheduling Policies on DRAM's Energy and Performance

Abstract In current scenario while designing a computing system it is necessary that detailed emphasis should be laid on two common goals, i.e ., increasing performance and decreasing power consumption. As we needto achieve either more performance at same power level or minimum power consumption for same performance level. Main memory of a system is one of the key resources that a program needs to run hence it acts as a major contributor towards both system's performance and power consumption. Main memory's performance depends on the way it accesses its contents. It is memory controller's access scheduler that decides which command to issue in every DRAM clock cycle on the basis of employed memory access scheduling policy. Based on underlying access strategy DRAM operations are scheduled in a way that it reduces DRAM's latency and power consumption by utilizing low power modes. In this paper, we have compared and analysedvarious memory access scheduling algorithms on the basis ofpage hit rate, energy-delay product, total execution time and maximum slowdown time. This analysis contributes to better understand how the performance and energy consumption of DRAM memory system is affected by the underlying memory controller's scheduling policies.