Effect of Photo Misalignment on N-LDMOS Hot Carrier Device Reliability

Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices

[1]  Prasad Chaparala,et al.  Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[2]  B. Szelag,et al.  Architecture optimization of an N-channel LDMOS device dedicated to RF-power application , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[3]  G. Groeseneken,et al.  Hot-carrier degradation phenomena in lateral and vertical DMOS transistors , 2004, IEEE Transactions on Electron Devices.

[4]  Alessandro Moscatelli,et al.  LDMOS implementation in a 0.35 /spl mu/m BCD technology (BCD6) , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[5]  A. J. Mouthaan,et al.  Introductory invited paper Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations , 2000 .

[6]  B. Senapati,et al.  A two mask complementary LDMOS module integrated in a 0.25 /spl mu/m SiGe:C BiCMOS platform , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[7]  J. Smith,et al.  The optimization of LBC6 power/mixed-signal IC BiCMOS process , 2001, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212).

[8]  D. Brisbin,et al.  Design optimization of N-LDMOS transistor arrays for hot carrier lifetime enhancement , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[9]  Bin Wang,et al.  Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[10]  P. Moens,et al.  Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[11]  A. Strachan,et al.  Optimization of LDMOS array design for SOA and hot carrier lifetime , 2003, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..

[12]  A. Strachan,et al.  A trench-isolated power BiCMOS process with complementary high performance vertical bipolars , 2002, Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting.

[13]  V. O'Donovan,et al.  Hot carrier reliability of lateral DMOS transistors , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[14]  D. Brisbin,et al.  Electrical characteristics and reliability of extended drain voltage NMOS devices with multi-RESURF junction , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..