A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video

This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2∼328mW in decoding CIF∼HD1080 videos at 3.75∼30fps when operating at 1∼150MHz, respectively.

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